Design, modeling and optimization of ultra-low power hybrid NEMS/CMOS circuits

Design, modeling and optimization of ultra-low power hybrid NEMS/CMOS circuits

Internship Description

‚ÄčThe goal of this internship is to investigate the feasibility of a novel nanoelectromechanical switching technology for implementation of robust, reliable and energy-efficient integrated systems. This technology will use an advanced air-gap backend- of-the-line (BEOL) process, which allows for aggressive scaling of relay footprint and monolithic integration of relay and CMOS devices. A new circuit design paradigm should be developed for automated implementation of hybrid CMOS-NEM relay integrated circuits (ICs). Such ICs comprise NEM relay logic blocks, analog CMOS blocks, and mixed-mode blocks implemented with both relays and CMOS transistors, such as non-volatile memories, interfaces or data converters.

Faculty Name

Field of Study

‚ÄčElectrical Engineering